Add NvAPI support for PCIE Lanes

diff --git a/include/ext_nvapi.h b/include/ext_nvapi.h
index 2652daa..a52c278 100644 (file)
--- a/include/ext_nvapi.h
+++ b/include/ext_nvapi.h
@@ -396,6 +396,7 @@ NVAPI_INTERFACE NvAPI_GPU_GetTachReading(NvPhysicalGpuHandle hPhysicalGPU, NvU32
 NVAPI_INTERFACE NvAPI_GPU_GetCoolerSettings(NvPhysicalGpuHandle hPhysicalGpu, NvU32 coolerIndex, NV_GPU_COOLER_SETTINGS *pCoolerSettings);
 NVAPI_INTERFACE NvAPI_GPU_GetDynamicPstatesInfoEx(NvPhysicalGpuHandle hPhysicalGpu, NV_GPU_DYNAMIC_PSTATES_INFO_EX *pDynamicPstatesInfoEx);
 NVAPI_INTERFACE NvAPI_GPU_GetAllClockFrequencies(NvPhysicalGpuHandle hPhysicalGpu, NV_GPU_CLOCK_FREQUENCIES *pClkFreqs);
+NVAPI_INTERFACE NvAPI_GPU_GetCurrentPCIEDownstreamWidth(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pWidth);
 
 #ifdef __nvapi_success
     #undef __success
@@ -465,6 +466,7 @@ typedef int (*NVAPI_GPU_GETTACHREADING) (NvPhysicalGpuHandle, NvU32 *);
 typedef int (*NVAPI_GPU_GETCOOLERSETTINGS) (NvPhysicalGpuHandle, NvU32, NV_GPU_COOLER_SETTINGS *);
 typedef int (*NVAPI_GPU_GETDYNAMICPSTATESINFOEX) (NvPhysicalGpuHandle, NV_GPU_DYNAMIC_PSTATES_INFO_EX *);
 typedef int (*NVAPI_GPU_GETALLCLOCKFREQUENCIES) (NvPhysicalGpuHandle, NV_GPU_CLOCK_FREQUENCIES *);
+typedef int (*NVAPI_GPU_GETCURRENTPCIEDOWNSTREAMWIDTH) (NvPhysicalGpuHandle, NvU32 *);
 
 typedef struct
 {
@@ -480,6 +482,7 @@ typedef struct
   NVAPI_GPU_GETCOOLERSETTINGS NvAPI_GPU_GetCoolerSettings;
   NVAPI_GPU_GETDYNAMICPSTATESINFOEX NvAPI_GPU_GetDynamicPstatesInfoEx;
   NVAPI_GPU_GETALLCLOCKFREQUENCIES NvAPI_GPU_GetAllClockFrequencies;
+  NVAPI_GPU_GETCURRENTPCIEDOWNSTREAMWIDTH NvAPI_GPU_GetCurrentPCIEDownstreamWidth;
 
 } hm_nvapi_lib_t;
 
@@ -498,6 +501,7 @@ int hm_NvAPI_GPU_GetTachReading (NVAPI_PTR *nvapi, NvPhysicalGpuHandle hPhysical
 int hm_NvAPI_GPU_GetCoolerSettings (NVAPI_PTR *nvapi, NvPhysicalGpuHandle hPhysicalGpu, NvU32 coolerIndex, NV_GPU_COOLER_SETTINGS *pCoolerSettings);
 int hm_NvAPI_GPU_GetDynamicPstatesInfoEx (NVAPI_PTR *nvapi, NvPhysicalGpuHandle hPhysicalGpu, NV_GPU_DYNAMIC_PSTATES_INFO_EX *pDynamicPstatesInfoEx);
 int hm_NvAPI_GPU_GetAllClockFrequencies (NVAPI_PTR *nvapi, NvPhysicalGpuHandle hPhysicalGpu, NV_GPU_CLOCK_FREQUENCIES *pClkFreqs);
+int hm_NvAPI_GPU_GetCurrentPCIEDownstreamWidth (NVAPI_PTR *nvapi, NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pWidth);
 
 #endif // HAVE_HWMON && HAVE_NVAPI
 

diff --git a/src/ext_nvapi.c b/src/ext_nvapi.c
index 85e45c5..a874847 100644 (file)
--- a/src/ext_nvapi.c
+++ b/src/ext_nvapi.c
@@ -27,16 +27,17 @@ int nvapi_init (NVAPI_PTR *nvapi)
     return (-1);
   }
 
-  HC_LOAD_FUNC(nvapi, nvapi_QueryInterface,               NVAPI_QUERYINTERFACE,               NVAPI,                0)
-  HC_LOAD_ADDR(nvapi, NvAPI_Initialize,                   NVAPI_INITIALIZE,                   nvapi_QueryInterface, 0x0150E828, NVAPI, 0)
-  HC_LOAD_ADDR(nvapi, NvAPI_Unload,                       NVAPI_UNLOAD,                       nvapi_QueryInterface, 0xD22BDD7E, NVAPI, 0)
-  HC_LOAD_ADDR(nvapi, NvAPI_GetErrorMessage,              NVAPI_GETERRORMESSAGE,              nvapi_QueryInterface, 0x6C2D048C, NVAPI, 0)
-  HC_LOAD_ADDR(nvapi, NvAPI_GPU_GetDynamicPstatesInfoEx,  NVAPI_GPU_GETDYNAMICPSTATESINFOEX,  nvapi_QueryInterface, 0x60DED2ED, NVAPI, 0)
-  HC_LOAD_ADDR(nvapi, NvAPI_EnumPhysicalGPUs,             NVAPI_ENUMPHYSICALGPUS,             nvapi_QueryInterface, 0xE5AC921F, NVAPI, 0)
-  HC_LOAD_ADDR(nvapi, NvAPI_GPU_GetThermalSettings,       NVAPI_GPU_GETTHERMALSETTINGS,       nvapi_QueryInterface, 0xE3640A56, NVAPI, 0)
-  HC_LOAD_ADDR(nvapi, NvAPI_GPU_GetTachReading,           NVAPI_GPU_GETTACHREADING,           nvapi_QueryInterface, 0x5F608315, NVAPI, 0)
-  HC_LOAD_ADDR(nvapi, NvAPI_GPU_GetCoolerSettings,        NVAPI_GPU_GETCOOLERSETTINGS,        nvapi_QueryInterface, 0xDA141340, NVAPI, 0)
-  HC_LOAD_ADDR(nvapi, NvAPI_GPU_GetAllClockFrequencies,   NVAPI_GPU_GETALLCLOCKFREQUENCIES,   nvapi_QueryInterface, 0xDCB616C3, NVAPI, 0)
+  HC_LOAD_FUNC(nvapi, nvapi_QueryInterface,                     NVAPI_QUERYINTERFACE,                     NVAPI,                0)
+  HC_LOAD_ADDR(nvapi, NvAPI_Initialize,                         NVAPI_INITIALIZE,                         nvapi_QueryInterface, 0x0150E828, NVAPI, 0)
+  HC_LOAD_ADDR(nvapi, NvAPI_Unload,                             NVAPI_UNLOAD,                             nvapi_QueryInterface, 0xD22BDD7E, NVAPI, 0)
+  HC_LOAD_ADDR(nvapi, NvAPI_GetErrorMessage,                    NVAPI_GETERRORMESSAGE,                    nvapi_QueryInterface, 0x6C2D048C, NVAPI, 0)
+  HC_LOAD_ADDR(nvapi, NvAPI_GPU_GetDynamicPstatesInfoEx,        NVAPI_GPU_GETDYNAMICPSTATESINFOEX,        nvapi_QueryInterface, 0x60DED2ED, NVAPI, 0)
+  HC_LOAD_ADDR(nvapi, NvAPI_EnumPhysicalGPUs,                   NVAPI_ENUMPHYSICALGPUS,                   nvapi_QueryInterface, 0xE5AC921F, NVAPI, 0)
+  HC_LOAD_ADDR(nvapi, NvAPI_GPU_GetThermalSettings,             NVAPI_GPU_GETTHERMALSETTINGS,             nvapi_QueryInterface, 0xE3640A56, NVAPI, 0)
+  HC_LOAD_ADDR(nvapi, NvAPI_GPU_GetTachReading,                 NVAPI_GPU_GETTACHREADING,                 nvapi_QueryInterface, 0x5F608315, NVAPI, 0)
+  HC_LOAD_ADDR(nvapi, NvAPI_GPU_GetCoolerSettings,              NVAPI_GPU_GETCOOLERSETTINGS,              nvapi_QueryInterface, 0xDA141340, NVAPI, 0)
+  HC_LOAD_ADDR(nvapi, NvAPI_GPU_GetAllClockFrequencies,         NVAPI_GPU_GETALLCLOCKFREQUENCIES,         nvapi_QueryInterface, 0xDCB616C3, NVAPI, 0)
+  HC_LOAD_ADDR(nvapi, NvAPI_GPU_GetCurrentPCIEDownstreamWidth,  NVAPI_GPU_GETCURRENTPCIEDOWNSTREAMWIDTH,  nvapi_QueryInterface, 0xD048C3B1, NVAPI, 0)
 
   return 0;
 }
@@ -205,6 +206,24 @@ int hm_NvAPI_GPU_GetAllClockFrequencies (NVAPI_PTR *nvapi, NvPhysicalGpuHandle h
   return NvAPI_rc;
 }
 
+int hm_NvAPI_GPU_GetCurrentPCIEDownstreamWidth (NVAPI_PTR *nvapi, NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pWidth)
+{
+  if (!nvapi) return (-1);
+
+  NvAPI_Status NvAPI_rc = nvapi->NvAPI_GPU_GetCurrentPCIEDownstreamWidth (hPhysicalGpu, pWidth);
+
+  if (NvAPI_rc != NVAPI_OK)
+  {
+    NvAPI_ShortString string = { 0 };
+
+    hm_NvAPI_GetErrorMessage (nvapi, NvAPI_rc, string);
+
+    log_info ("WARN: %s %d %s\n", "NvAPI_GPU_GetCurrentPCIEDownstreamWidth()", NvAPI_rc, string);
+  }
+
+  return NvAPI_rc;
+}
+
 #ifdef __MINGW64__
 
 void __security_check_cookie (uintptr_t _StackCookie)

diff --git a/src/shared.c b/src/shared.c
index cd60e25..b3b1d0d 100644 (file)
--- a/src/shared.c
+++ b/src/shared.c
@@ -3264,7 +3264,11 @@ int hm_get_buslanes_with_device_id (const uint device_id)
     #endif
 
     #if defined(WIN) && defined(HAVE_NVAPI)
+    int Width;
 
+    if (hm_NvAPI_GPU_GetCurrentPCIEDownstreamWidth (data.hm_nv, data.hm_device[device_id].adapter_index.nv, (NvU32 *) &Width) != NVAPI_OK) return -1;
+
+    return Width;
     #endif
   }
   #endif // HAVE_NVML || HAVE_NVAPI