#ifndef EXT_NVAPI_H
#define EXT_NVAPI_H
-#if defined(HAVE_HWMON) && defined(HAVE_NVAPI)
+#if defined(HAVE_HWMON)
#include <common.h>
#define NV_GPU_DYNAMIC_PSTATES_INFO_EX_VER MAKE_NVAPI_VERSION(NV_GPU_DYNAMIC_PSTATES_INFO_EX,1)
#define NVAPI_MAX_COOLER_PER_GPU 20
+
#define GPU_COOLER_SETTINGS_VER 0x20000
+#define GPU_COOLER_LEVELS_VER 0x10000
// Used in NV_GPU_COOLER_SETTINGS
typedef struct
} NV_GPU_COOLER_SETTINGS;
+typedef struct
+{
+ NvS32 Level;
+ NvS32 Policy;
+
+} NvLevel;
+
+typedef struct
+{
+ NvU32 Version;
+ NvLevel Levels[NVAPI_MAX_COOLER_PER_GPU];
+
+} NV_GPU_COOLER_LEVELS;
+
+#define NVAPI_MAX_GPU_PUBLIC_CLOCKS 32
+
+typedef enum _NV_GPU_PUBLIC_CLOCK_ID
+{
+ NVAPI_GPU_PUBLIC_CLOCK_GRAPHICS = 0,
+ NVAPI_GPU_PUBLIC_CLOCK_MEMORY = 4,
+ NVAPI_GPU_PUBLIC_CLOCK_PROCESSOR = 7,
+ NVAPI_GPU_PUBLIC_CLOCK_VIDEO = 8,
+ NVAPI_GPU_PUBLIC_CLOCK_UNDEFINED = NVAPI_MAX_GPU_PUBLIC_CLOCKS,
+} NV_GPU_PUBLIC_CLOCK_ID;
+
+//! Used in NvAPI_GPU_GetAllClockFrequencies()
+typedef struct
+{
+ NvU32 version; //!< Structure version
+ NvU32 reserved; //!< These bits are reserved for future use.
+ struct
+ {
+ NvU32 bIsPresent:1; //!< Set if this domain is present on this GPU
+ NvU32 reserved:31; //!< These bits are reserved for future use.
+ NvU32 frequency; //!< Clock frequency (kHz)
+ }domain[NVAPI_MAX_GPU_PUBLIC_CLOCKS];
+} NV_GPU_CLOCK_FREQUENCIES_V1;
+
+//! Used in NvAPI_GPU_GetAllClockFrequencies()
+typedef enum
+{
+ NV_GPU_CLOCK_FREQUENCIES_CURRENT_FREQ = 0,
+ NV_GPU_CLOCK_FREQUENCIES_BASE_CLOCK = 1,
+ NV_GPU_CLOCK_FREQUENCIES_BOOST_CLOCK = 2,
+ NV_GPU_CLOCK_FREQUENCIES_CLOCK_TYPE_NUM = 3
+} NV_GPU_CLOCK_FREQUENCIES_CLOCK_TYPE;
+
+//! Used in NvAPI_GPU_GetAllClockFrequencies()
+typedef struct
+{
+ NvU32 version; //!< Structure version
+ NvU32 ClockType:2; //!< One of NV_GPU_CLOCK_FREQUENCIES_CLOCK_TYPE. Used to specify the type of clock to be returned.
+ NvU32 reserved:22; //!< These bits are reserved for future use. Must be set to 0.
+ NvU32 reserved1:8; //!< These bits are reserved.
+ struct
+ {
+ NvU32 bIsPresent:1; //!< Set if this domain is present on this GPU
+ NvU32 reserved:31; //!< These bits are reserved for future use.
+ NvU32 frequency; //!< Clock frequency (kHz)
+ }domain[NVAPI_MAX_GPU_PUBLIC_CLOCKS];
+} NV_GPU_CLOCK_FREQUENCIES_V2;
+
+//! \ingroup gpuclock
+//! Used in NvAPI_GPU_GetAllClockFrequencies()
+typedef NV_GPU_CLOCK_FREQUENCIES_V2 NV_GPU_CLOCK_FREQUENCIES;
+
+//! \addtogroup gpuclock
+//! @{
+#define NV_GPU_CLOCK_FREQUENCIES_VER_1 MAKE_NVAPI_VERSION(NV_GPU_CLOCK_FREQUENCIES_V1,1)
+#define NV_GPU_CLOCK_FREQUENCIES_VER_2 MAKE_NVAPI_VERSION(NV_GPU_CLOCK_FREQUENCIES_V2,2)
+#define NV_GPU_CLOCK_FREQUENCIES_VER_3 MAKE_NVAPI_VERSION(NV_GPU_CLOCK_FREQUENCIES_V2,3)
+#define NV_GPU_CLOCK_FREQUENCIES_VER NV_GPU_CLOCK_FREQUENCIES_VER_3
+//! @}
+
+//! Used in NvAPI_GPU_GetPerfDecreaseInfo.
+//! Bit masks for knowing the exact reason for performance decrease
+typedef enum _NVAPI_GPU_PERF_DECREASE
+{
+ NV_GPU_PERF_DECREASE_NONE = 0, //!< No Slowdown detected
+ NV_GPU_PERF_DECREASE_REASON_THERMAL_PROTECTION = 0x00000001, //!< Thermal slowdown/shutdown/POR thermal protection
+ NV_GPU_PERF_DECREASE_REASON_POWER_CONTROL = 0x00000002, //!< Power capping / pstate cap
+ NV_GPU_PERF_DECREASE_REASON_AC_BATT = 0x00000004, //!< AC->BATT event
+ NV_GPU_PERF_DECREASE_REASON_API_TRIGGERED = 0x00000008, //!< API triggered slowdown
+ NV_GPU_PERF_DECREASE_REASON_INSUFFICIENT_POWER = 0x00000010, //!< Power connector missing
+ NV_GPU_PERF_DECREASE_REASON_UNKNOWN = 0x80000000, //!< Unknown reason
+} NVAPI_GPU_PERF_DECREASE;
+
+
NVAPI_INTERFACE NvAPI_QueryInterface(uint offset);
NVAPI_INTERFACE NvAPI_Initialize();
NVAPI_INTERFACE NvAPI_Unload();
NVAPI_INTERFACE NvAPI_GPU_GetThermalSettings(NvPhysicalGpuHandle hPhysicalGpu, NvU32 sensorIndex, NV_GPU_THERMAL_SETTINGS *pThermalSettings);
NVAPI_INTERFACE NvAPI_GPU_GetTachReading(NvPhysicalGpuHandle hPhysicalGPU, NvU32 *pValue);
NVAPI_INTERFACE NvAPI_GPU_GetCoolerSettings(NvPhysicalGpuHandle hPhysicalGpu, NvU32 coolerIndex, NV_GPU_COOLER_SETTINGS *pCoolerSettings);
+NVAPI_INTERFACE NvAPI_GPU_SetCoolerLevels(NvPhysicalGpuHandle hPhysicalGpu, NvU32 coolerIndex, NV_GPU_COOLER_LEVELS *pCoolerLevels);
NVAPI_INTERFACE NvAPI_GPU_GetDynamicPstatesInfoEx(NvPhysicalGpuHandle hPhysicalGpu, NV_GPU_DYNAMIC_PSTATES_INFO_EX *pDynamicPstatesInfoEx);
+NVAPI_INTERFACE NvAPI_GPU_GetAllClockFrequencies(NvPhysicalGpuHandle hPhysicalGpu, NV_GPU_CLOCK_FREQUENCIES *pClkFreqs);
+NVAPI_INTERFACE NvAPI_GPU_GetCurrentPCIEDownstreamWidth(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pWidth);
+NVAPI_INTERFACE NvAPI_GPU_GetPerfDecreaseInfo(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pPerfDecrInfo);
#ifdef __nvapi_success
#undef __success
typedef int (*NVAPI_GPU_GETTHERMALSETTINGS) (NvPhysicalGpuHandle, NvU32, NV_GPU_THERMAL_SETTINGS *);
typedef int (*NVAPI_GPU_GETTACHREADING) (NvPhysicalGpuHandle, NvU32 *);
typedef int (*NVAPI_GPU_GETCOOLERSETTINGS) (NvPhysicalGpuHandle, NvU32, NV_GPU_COOLER_SETTINGS *);
+typedef int (*NVAPI_GPU_SETCOOLERLEVELS) (NvPhysicalGpuHandle, NvU32, NV_GPU_COOLER_LEVELS *);
typedef int (*NVAPI_GPU_GETDYNAMICPSTATESINFOEX) (NvPhysicalGpuHandle, NV_GPU_DYNAMIC_PSTATES_INFO_EX *);
+typedef int (*NVAPI_GPU_GETALLCLOCKFREQUENCIES) (NvPhysicalGpuHandle, NV_GPU_CLOCK_FREQUENCIES *);
+typedef int (*NVAPI_GPU_GETCURRENTPCIEDOWNSTREAMWIDTH) (NvPhysicalGpuHandle, NvU32 *);
+typedef int (*NVAPI_GPU_GETPERFDECREASEINFO) (NvPhysicalGpuHandle, NvU32 *);
typedef struct
{
NVAPI_GPU_GETTHERMALSETTINGS NvAPI_GPU_GetThermalSettings;
NVAPI_GPU_GETTACHREADING NvAPI_GPU_GetTachReading;
NVAPI_GPU_GETCOOLERSETTINGS NvAPI_GPU_GetCoolerSettings;
+ NVAPI_GPU_SETCOOLERLEVELS NvAPI_GPU_SetCoolerLevels;
NVAPI_GPU_GETDYNAMICPSTATESINFOEX NvAPI_GPU_GetDynamicPstatesInfoEx;
+ NVAPI_GPU_GETALLCLOCKFREQUENCIES NvAPI_GPU_GetAllClockFrequencies;
+ NVAPI_GPU_GETCURRENTPCIEDOWNSTREAMWIDTH NvAPI_GPU_GetCurrentPCIEDownstreamWidth;
+ NVAPI_GPU_GETPERFDECREASEINFO NvAPI_GPU_GetPerfDecreaseInfo;
} hm_nvapi_lib_t;
int hm_NvAPI_GPU_GetThermalSettings (NVAPI_PTR *nvapi, NvPhysicalGpuHandle hPhysicalGpu, NvU32 sensorIndex, NV_GPU_THERMAL_SETTINGS *pThermalSettings);
int hm_NvAPI_GPU_GetTachReading (NVAPI_PTR *nvapi, NvPhysicalGpuHandle hPhysicalGPU, NvU32 *pValue);
int hm_NvAPI_GPU_GetCoolerSettings (NVAPI_PTR *nvapi, NvPhysicalGpuHandle hPhysicalGpu, NvU32 coolerIndex, NV_GPU_COOLER_SETTINGS *pCoolerSettings);
+int hm_NvAPI_GPU_SetCoolerLevels (NVAPI_PTR *nvapi, NvPhysicalGpuHandle hPhysicalGpu, NvU32 coolerIndex, NV_GPU_COOLER_LEVELS *pCoolerLevels);
int hm_NvAPI_GPU_GetDynamicPstatesInfoEx (NVAPI_PTR *nvapi, NvPhysicalGpuHandle hPhysicalGpu, NV_GPU_DYNAMIC_PSTATES_INFO_EX *pDynamicPstatesInfoEx);
+int hm_NvAPI_GPU_GetAllClockFrequencies (NVAPI_PTR *nvapi, NvPhysicalGpuHandle hPhysicalGpu, NV_GPU_CLOCK_FREQUENCIES *pClkFreqs);
+int hm_NvAPI_GPU_GetCurrentPCIEDownstreamWidth (NVAPI_PTR *nvapi, NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pWidth);
+int hm_NvAPI_GPU_GetPerfDecreaseInfo (NVAPI_PTR *nvapi, NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pPerfDecrInfo);
-#endif // HAVE_HWMON && HAVE_NVAPI
+#endif // HAVE_HWMON
#endif // EXT_NVAPI_H
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